In the previous set of posts, I attempted to get an Amiga FPGA implementation to run on a Zybo board.
My attempts started off to look promising, getting an Motorola 68K to run on the FPGA.
However, in the last couple of months, I hit a brick wall: Memory latency. As you might know, the memory of an Amiga clocks at a speed of 7MHz. On the Zybo board, however, I was experiencing latency limiting my access to memory to 5MHz.
At this point, I just would like to point out that I don't have anything against the Zybo board. It is just that in order to properly utilise memory on the Zybo board, and any modern computer system, for that matter, you need to access memory in a pipelined matter, and use some caches.
Compared to modern day systems, the Amiga accesses memory in quite a random fashion, so caching would not really benefit the core of operation of an Amiga.
In this post I will unpack this limitation of memory latency a bit more, and I will give some pointers on which direction I am going to take to try and get around this issue.
More on the issue of latency
In my journey on creating an Amiga on the Zybo, I had been looking at the MiSTer project quite a bit:
There was one paragraph on the wiki page, which, if I have seen it originally, might have saved me some pain:
(recommended expansion) – This small board plugs into the GPIO0 connector of the DE10-nano board. Whilst the DE10-nano has fast DDR3 memory, it cannot be used to emulate a retro EDO DRAM due to a high latency and shared usage from the ARM side. This SDR SDRAM on a daughter board is required for most cores to emulate a retro memory module.
This actually also applies to the Zybo board, and since there is not really a way to add an SDRAM module to the Zybo board, the Zybo board is not really suited for emulating an Amiga within the FPGA.
Using an alternative board
With the Zybo board that is out of the question for what we want to do, I thought long and hard on what board I can use for this exercise.
What we are looking for, is a board that will provide as much direct access between the FPGA and RAM as possible. This will allow us to optimise and reduce latency for our kind of RAM access patterns.
From the MiSTer wiki, as I mentioned in the previous section, they indicated that the emulated cores uses SDRAM and that DDR3 RAM is not really suitable. What is not clear though, is if the majority is due to the DDR3 RAM, or what amount the shared ARM side contributes to the latency.
If it is true that DDR3 RAM just by itself gives unacceptable latency for an Amiga implementation, then this would immediately eliminate quite a number of FPGA's that could be used for this exercise.
It would be nice if we can get some ballpark figure for DDR3 latency, to see, at least in theory, if it would be possible to run an Amiga core with DDR3 memory.
One brand of memory where the DDR3 timings is readily available in their datasheets, is Micron. Firstly, reading to this link, a good estimate for latency based on DDR timings, would be the following formula:
TRP + TRCD + CL
Peaking at one of the datasheets of Micron, it seems that a typical value for adding these numbers together, is around 39ns. So, if, for each memory access there is a delay of 39ns, we are looking at a memory speed of about 25MHz.
So, it seems that we might be ok, at least in theory, when using DDR3 memory for emulating an Amiga core. That been said, this assumes we can control how the data is accessed from DDR3 memory.
I am going to take a gamble on this, and see how far I am going to get implementing an Amiga on another FPGA board that support direct access to DDR3 memory.
The question is: which board? The board I have in mind is the Arty-A7 development board, from Digilent: