When I was developing a C64 to run on an FPGA on the Zybo board, I exclusively used Vivado 2017.1.
However, during the course of this blog series, I got feedback from a couple of readers saying that they cannot build the source code from this project on later versions of Vivado.
So, in this post of I thought it would be rather interesting to see how the source code of this project wil behave on the latest version of Vivado.
What is the latest version of Vivado?
I wanted to get hold of the latest version of Vivado so I visited Xilinx's website.
On their website I found that the latest version was 2020.1, but it had no free version.
For the sake of clarity, free versions of Vivado usually have the word WebPack in there name and you will only get a subset of the functionality provided by a full version of Vivado.
Eventually I found that the latest free version of Vivado WebPack is 2019.1. This is the version we will be using in this post.
Issues experienced
When I opened the project in Vivado 2019.1, Vivado did quite a good job upgrading the IP's used in my design to the latest version.
This didn't go without any issues, though.
For a start, I got a number of issues with the two Clock wizard blocks in my design. One of the issues I was having, was that one of these blocks outputting two clock frequencies, ended off outputting only one frequency in Vivado 2019.1
In the the end I just deleted the two clock wizard blocks, created new ones and wire them up again.
Another minor issue experienced was that the Zynq block didn't had the I2C port 1 enabled, which I use to enable sound on the Zybo board. For this I also had to enable I2C port and wire up the ports.
One final issue I had, was when generating the Bitstream. The IDE complained about one of the AXI ports not been connected, due to optimisation.
I can remember I has a similar issue right in the beginning of the series when I was playing with AXI ports. At that time the issue I was having was with port AXI_ARID. The way I fixed that issue was just to wire AXI_ARID to a logic zero.
In Vivado 2019.1, the issue was the port AXI_AWID. Two very similar ports. The former port specifies the ID for an AXI read transaction, and the latter is for a ID for a write transaction. It is just funny that Vivado 2017.1 also didn't complain at the time about the AXI_AWID port.
Anyway, I fixed the AXI_AWID error by also wiring it to a logic 0.
Building the source in Vivado 2019.1
I have made the changes available on my GitHub repo for this project, which will enable you to build the project with Vivado 2019.1. For the record, here is the link again to the project repo on GitHub:
I wanted to retain the code that enables one to build the source on Vivado 2017.1, so I made the 2019.1 changes available in a branch. So, just a summary of the branches:
- Master: Will build on Vivado 2017.1
- Branch v2019.1: This branch will build on Vivado 2019.1.
When building the code on Vivado 2019.1, you might experience some minor issues. So, in this section I will discuss these issues, together with how to get around them.
Before running Synthesise, it is advisable to create a new HDL wrapper. In doing this, Vivado will complain about some IP's that are locked. Vivado will alternatively suggest to run Check IP Report Status.
So, under the the Reports menu select IP Report Status. From the tab that opens up select Upgrade selected. Eventually a couple of processes will start that will generate all the missing sources, after which you should be able to synthesise and generate bitstream.
In Summary
In this post I discussed how the source code of our C64 FPGA implementation currently behaves in Vivado 2019.1 and the changes required to make it work.
Till next time!
