Blog Series Update: Source on Github Repo

Foreword

Good day all! In this post, I will not be doing a technical discussion, but rather a bit of an update on this Blog Series.

From almost the beginning of this Blog series, I maintained a Github Repository of the source code presented throughout the series.

I must confess that I haven't updated this repo with source code presented for quite a long time (more than a year!).

The reason for this is mainly because when working with Block Designs in Vivado, you end off with quite a bit of auto generated files during Synthesis, which can differ quite a bit from one synthesis run to the next.

This just made the whole exercise of maintaining changes on the Github repo quite a nightmare.

Also, what made matters worse, was that when you cloned the repo and try to synthesise the design, one always end off with some errors on the AXI blocks. Eventually you just end off deleting these AXI blocks, re-adding them in the block design, followed by wiring them up to the rest of the design.

In recent months I received quite a number queries from asking if I can update the source on my Github Repo.

So, in this lockdown period I am having in my country, and I belief many other countries around the world, I set forth to update update the Github Repo for this Blog series.

I also gave some thought into how to simplify the build process, which I will explain in this post.

Gearing up

Let us start this post by just giving the address again for the Github Repo that hosts the source code for this Blog Series:

https://github.com/ovalcode/c64fpga

This Repo also contains a readme telling you how to get the source code and how to build the project.

In this Readme I am also explaining the issue with AXI blocks as I explained in the Foreword.

It is here I found a way to improve the build process a bit. You will also start by running the tcl file to generate the project files, after which you will open the generated project.

Next you will start off the Synthesis of the project. As previously you will see quite a number of errors appearing, but just wait till the whole process completes.

Afterwards you IDE will something like the following:

Notice that at this point I have the Design Runs tab open showing that all Out-of-Context Runs that have failed.

This window showing the errors, will also give you the solution to fixing all these issues.

Now, right click on the first error node and select Open elaborated Design. The IDE will be busy for a minute or two, after which this node will change from an error icon to a check icon.

Next, one needs to following the same set of steps for the remaining items. There is about 13 of these items, so it will feel a bit cumbersome, taking about half an hour.

However, this only needs to be done once after a clone.

After finished doing the Open Eloborate design on all items, synthesis and Generate BitStream should work without an issue.

What the source code contains

At this point the Github Repo contains all the necessary sources for generating the FPGA bitstream you can use in the previous set of posts, that will give you a VGA output of the Linux console and optionally switching to the C64 screen.

If you would rather go directly to the C64 screen on power up, you can add a Constant block to the block design, supplying the value '1' to the C64_screen_mode port on the VGA block.

Currently, this Github doesn't provide source code that will generate the necessary ARM code for booting into Linux or a baremetal design. In the future, however, I might add the necessary source code for this to the GIT repo.

What is also missing from the source code is the IP block that send the generated SID audio to the sound chip on the Zybo board.

In Summary

In this post I have given an update on the source code for this Blog series on the Github Repo.

See you in the next post, and stay safe!